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E2C0035-27-Y4 Semiconductor
Semiconductor MSM9200-XX
GENERAL DESCRIPTION
This version: Nov. 1997 MSM9200-XX Previous version: Jul. 1996
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5 7 Dot Character 16-Digit Display Controller/Driver with Character RAM
The MSM9200-XX is a dot matrix vacuum fluorescent display tube controller driver IC which displays characters, numerics and symbols. Dot matrix vacuum fluorescent display tube drive signals are generated by serial data sent from a microcontroller. A display system is easily realized by internal ROM and RAM for character display. The MSM9200-XX has low power consumption because it is munufactured in CMOS process technology. -01 and -02 are available as general codes. Custom codes are provided if necessary.
FEATURES
* Logic power supply (VDD) : 3.3 V10%/5.0 V10% * Fluorescent display tube drive power supply (VDISP) : 3.3 V10%/5.0 V10% * Fluorescent display tube drive power supply (VFL) : -20 to -60 V * VFD driver output current (VFD driver output can directly be connected to the fluorescent display tube. No pull-down resistor is required.) - Segment driver (SEG1 to SEG35) : -5 mA (VFL=-60V) - Segment driver (AD1 to AD8) : -10 mA (VFL=-60V) - Grid driver (COM1 to COM16) : -30 mA (VFL=-60V) * General output port output current - Output driver (P1-4) : 1 mA (VDD=3.3V10%) 2 mA (VDD=5.0V10%) * Content of display - CGROM 57 dots, 224 types (character data) - CGRAM 57 dots, 32 types (character data) - ADRAM 16 (display digit) 8 bits (symbol data) - DCRAM 64 (stored digit) 8 bits (register for character data display) - General output port 4 bits (static mode) * Display control function - Display digit : 1 to 16 digits - Display duty (contrast adjustment) : 16 stages - Display blink position specification : Blinking time is input externally - Display shift (left and right) : Can be set only for SEG output - All lights ON/OFF * 4 interfaces with microcontroller : DA, CS, CP, and BLINK (5 interfaces when RESET is added) * 1 byte instruction execution (excluding data write to RAM and display blink position specification) * Oscillation circuit included (external C and R) * Package: 80-pin plastic QFP (QFP80-P-1414-0.65-K) (Product name: MSM9200-XXGS-K) xx indicated the code number. 1/34
Semiconductor
MSM9200-XX
BLOCK DIAGRAM
VDISP VDD GND VFL
BLINK DCRAM 64w8b CGROM 224w35b Segment Driver RESET DA CP CS 8-bit Shift Register CGRAM 32w35b ADRAM 16w8b SEG35 AD1 AD Driver AD8 SEG1
DCRAM Address Counter
Address Selector Command Decoder Control Circuit Write Address Counter Read Address Counter
P1 Port Driver P4 Digit Control Duty Control COM1 Grid Driver COM16
Timing Generator 1 OSC0 Oscillator OSC1
Timing Generator 2
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Semiconductor
MSM9200-XX
INPUT AND OUTPUT CONFIGURATION
Schematic Diagrams of Logic Portion Input and Output Circuits Input Pin
VDD VDD
INPUT
GND
GND
Output Pin
VDD VDD
OUTPUT
GND
GND
Schematic Diagram of Driver Output Circuit
VDISP VDISP
OUTPUT
VFL
VFL
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Semiconductor
PIN CONFIGURATION (TOP VIEW)
AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 VDISP1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
NC: No connection
80-Pin Plastic QFP
MSM9200-XX
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
VFL2 NC VDISP3 NC P4 P3 P2 P1 GND OSC0 OSC1 RESET BLINK DA CP CS VDD VDISP2 NC VFL1
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 SEG35 SEG34 SEG33 SEG32
SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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Semiconductor
MSM9200-XX
PIN DESCRIPTION
Pin 10 to 44 Symbol SEG1-35 Type Connects to: O tube grid electrode 45 to 60 COM1-16 O tube grid electrode 1 to 8 AD1-8 O tube grid electrode LED drive 73 to 76 64 9, 63, 78 72 61, 80 67 66 65 P1-4 VDD VDISP1-3 GND VFL1-2 DA CP CS O -- -- -- -- I I I Microcontroller Microcontroller Microcontroller control terminals Power supply Description Directly connected to fluorescent display tube and a pull-down resistor is not necessary. IOH>-5 mA Directly connected to fluorescent display tube and a pull-down resistor is not necessary. IOH>-30 mA Directly connected to fluorescent display tube and a pull-down resistor is not necessary. IOH>-10 mA General port output. Output of these pins in static mode, so control for LED driving is performed through these pins. VDD-GND are power supplies for internal logic. VDISP-VFL are power supplies for driving fluorescent tubes. Use the same power supply for VDD and VDISP. Apply VFL after VDD and VDISP are applied. Serial data input (positive logic). Input from LSB. Shift clock input. Serial data is shifted on the rising edge of CP. Chip select input. "H" disables serial data transfer. Display blink frequency input (square wave). Only the position specified by the display blink position set command 68 BLINK I Microcontroller is validated. The time of "High" (light ON) and "Low" (light OFF) level of the signal frequency to be input to BLINK is the blink time. Fix BLINK pin to the VDD or GND pin when the display blink control is not used.
Fluorescent Fluorescent display tube anode electrode drive output.
Fluorescent Fluorescent display tube grid electrode drive output.
Fluorescent Fluorescent display tube grid electrode drive output.
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Semiconductor
MSM9200-XX
Pin
Symbol
Type Connects to:
Description Reset input (pull-up resistor included). "Low" initializes all the functions. Initial status is as follows. * Address of each RAM * Data of each RAM address "00"H Content is undefined 16 digits 0/16 Blinking is disabled for all outputs OFF mode "Low" level (Circuit when R and C are connected externally) C2 R2 See Application Circuit.
Micro69 RESET I or C2, R2
* Display digit * Display blink * All lights ON or OFF * All outputs RESET
controller * Contrast adjusment
External RC pin for RC oscillation. 71 OSC0 I C1, R1 70 OSC1 O Connect R and C externally. The RC time constant depends on the VDD voltage used. Set the target oscillation frequency to 2 MHz. OSC0 R1 OSC1 C1 (RC oscillation circuit) See Application Circuit.
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Semiconductor
MSM9200-XX
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage 1 Supply Voltage 2 Input Voltage Power Dissipation Storage Temperature Symbol VDD VDISP VFL VIN PD TSTG IO1 Output Current IO2 IO3 IO4 Condition (*1) (*1) -- -- Ta25C -- COM1-COM16 AD1-AD8 SEG1-SEG35 P1-P4 Rating -0.3 to 6.5 -0.3 to 6.5 -80 to VDISP+0.3 -80 to VDD+0.3 565 -55 to 150 -40 to 0.0 -20 to 0.0 -10 to 0.0 -4.0 to 4.0 mA Unit V V V V mW C
*1 Use the same power supply for VDD and VDISP.
RECOMMENDED OPERATING CONDITIONS-1
When the power supply voltage is 5V (typ).
Parameter Supply Voltage 1 Supply Voltage 2 High Level Input Voltage Low Level Input Voltage CP Frequency Oscillation Frequency Frame Frequency RESET Input Time Operating Temperature Symbol VDD VDISP VFL VIH VIL fC fOSC fFR tRSON TOP Condition -- -- All input pins excluding OSC0 pin -- R1=3.3kW, C1=47pF
DIGIT=1-16, R1=3.3kW, C1=47pF
Min. 4.5 -60 -- -- 1.5 183 0 -40
Typ. 5.0 -- -- -- -- 2.0 244 -- --
Max. 5.5 -20 -- 0.3VDD 1.0 2.5 305 200 85
Unit V V V V MHz MHz Hz s C
All input pins excluding OSC0 pin 0.7VDD
R2=1.0kW, C2=0.1PF --
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Semiconductor
MSM9200-XX
RECOMMENDED OPERATING CONDITIONS-2
When the power supply voltage is 3.3V (typ).
Parameter Supply Voltage 1 Supply Voltage 2 High Level Input Voltage Low Level Input Voltage CP Frequency Oscillation Frequency Frame Frequency RESET Input Time Operating Temperature Symbol VDD VDISP VFL VIH VIL fC fOSC fFR tRSON TOP Condition -- -- All input pins excluding OSC0 pin -- R1=3.3kW, C1=39pF
DIGIT=1-16, R1=3.3kW, C1=39pF
Min. 3.0 -60 -- -- 1.5 183 0 -40
Typ. 3.3 -- -- -- -- 2.0 244 -- --
Max. 3.6 -20 -- 0.2VDD 1.0 2.5 305 200 85
Unit V V V V MHz MHz Hz s C
All input pins excluding OSC0 pin 0.8VDD
R2=1.0kW, C2=0.1F --
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Semiconductor
MSM9200-XX
ELECTRICAL CHARACTERISTICS
DC Characteristics-1
(VDD=VDISP=5.0V10%, VFL=-60V, Ta=-40 to +85C, unless otherwise specified) Parameter High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Symbol VIH VIL IIH IIL VOH1 High Level Output Voltage VOH2 VOH3 VOH4 Low Level Output Voltage VOL2 IDD1 Current Consumption IDD2 VDD, VDISP VOL1 Applied pin CS, CP, BLINK, DA, RESET CS, CP, BLINK, DA, RESET CS, CP, BLINK, DA, RESET CS, CP, BLINK, DA, RESET COM1-16 AD1-8 SEG1-35 P1-4 COM1-16 AD1-8 SEG1-35 P1-4 IOL1=2mA Duty=15/16 fOSC= 2MHz no load Digit=1-16 All output lights ON Duty=8/16 Digit=1-9 All output lights OFF -- 3 mA -- 4 mA -- 1.0 V -- -- VFL+1.0 V Condition -- -- VIH=VDD VIL=0.0V IOH1=-30mA IOH2=-10mA IOH3=-5mA IOH4=-2mA Min. 0.7VDD -- -1.0 -1.0 VDISP-1.5 VDISP-1.5 VDISP-1.5 VDD-1.0 Max. -- 0.3VDD 1.0 1.0 -- -- -- -- Unit V V A A V V V V
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Semiconductor DC Characteristics-2
MSM9200-XX
(VDD=VDISP=3.3V10%, VFL=-60V, Ta=-40 to +85C, unless otherwise specified) Parameter High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Symbol VIH VIL IIH IIL VOH1 High Level Output Voltage VOH2 VOH3 VOH4 Low Level Output Voltage VOL2 IDD1 Current Consumption IDD2 VDD, VDISP VOL1 Applied pin CS, CP, BLINK, DA, RESET CS, CP, BLINK, DA, RESET CS, CP, BLINK, DA, RESET CS, CP, BLINK, DA, RESET COM1-16 AD1-8 SEG1-35 P1-4 COM1-16 AD1-8 SEG1-35 P1-4 IOL1=1mA Duty=15/16 fOSC= 2MHz no load Digit=1-16 All output lights ON Duty=8/16 Digit=1-9 All output lights OFF -- 2 mA -- 3 mA -- 1.0 V -- -- VFL+1.0 V Condition -- -- VIH=VDD VIL=0.0V IOH1=-30mA IOH2=-10mA IOH3=-5mA IOH4=-1mA Min. 0.8VDD 0.0 -1.0 -1.0 VDISP-1.5 VDISP-1.5 VDISP-1.5 VDD-1.0 Max. -- 0.2VDD 1.0 1.0 -- -- -- -- Unit V V A A V V V V
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Semiconductor AC Characteristics-1
MSM9200-XX
(VDD, VDISP=5.0V10%, VFL=-60V, Ta=-40 to +85C, unless otherwise specified) Parameter Symbol Condition -- -- -- -- -- R1=3.3kW, C1=47PF -- R1=3.3kW, C1=47PF Min. -- 300 300 300 300 16 300 8 300 300 tR=20% to 80% tF=80% to 20% -- -- -- 5.0 Max. 1.0 -- -- -- -- -- -- -- -- -- 4.0 4.0 100 -- Unit MHz ns ns ns ns ms ns ms ns ms ms ms ms ms
CP Frequncy
CP Pulse Width DA Setup Time DA Hold Time CS Setup Time CS Hold Time CS Wait Time Data Processing Time RESET Pulse Width Waite DA Time All Output Slow Rate VDD Rise Time VDD Off Time
fC
tCW tDS tDH tCSS tCSH tCSW tDOFF tRSON tRSOFF tR tF tPRZ tPOF Cl=100pF
When RESET signal is input externally
--
When mounted in the unit When mounted in the unit, VDD=0.0V
AC Characteristics-2
(VDD, VDISP=3.3V10%, VFL=-60V, Ta=-40 to +85C, unless otherwise specified) Parameter CP Frequncy CP Pulse Width DA Setup Time DA Hold Time CS Setup Time CS Hold Time CS Wait Time Data Processing Time RESET Pulse Width DA Wait Time All Output Slew Rate VDD Rise Time VDD Off Time Symbol fC tCW tDS tDH tCSS tCSH tCSW tDOFF tWRES tRSOFF tR tF tPRZ tPOF Cl=100pF Condition -- -- -- -- -- R1=3.3kW, C1=39PF -- R1=3.3kW, C1=39PF When RESET signal is input externally -- tR=20% to 80% tF=80% to 20% Min. -- 300 300 300 300 16 300 8 300 300 -- -- -- 5.0 Max. 1.0 -- -- -- -- -- -- -- -- -- 4.0 4.0 100 -- Unit MHz ns ns ns ns ms ns ms ns ms ms ms ms ms
When mounted in the unit When mounted in the unit, VDD=0.0V
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Semiconductor
MSM9200-XX
TIMING DIAGRAM
* Data Timing
tCSS CS tC CP tDS DA VALID VALID tDOFF tDH VALID VALID VIH VIL fC tCW tCW tCSH VIH VIL tCSW VIH VIL
* Reset Timing
0.8 VDD 0.0 V VIH 0.5 VDD VIL VIH VIL
VDD RESET
tPRZ tRSON tRSOFF
=
tOF
When input externally
tWRES
When external R and C are connected.
tRSOFF DA
* Output Timing
All outputs
tR
tF
0.8 VDISP 0.2 VFL
Symbol VIH VIL
VDD=3.3V10% 0.8 VDD 0.2 VDD
VDD=5.0V10% 0.7 VDD 0.3 VDD
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Semiconductor
MSM9200-XX
FUNCTIONAL DESCRIPTION
Command List
LSB
Command 1 DCRAM data write 1 2 DCRAM data write 2 3 DCRAM data write 3 4 DCRAM data write 4
1st byte B1 X1 X1 X1 X1 B2 X2 X2 X2 X2 B3 X3 X3 X3 X3 B4 1 0 1 0 B5 0 1 1 0 B6 0 0 0 1
MSB
LSB
2nd byte B1 C1 C1 C1 C1 B2 C2 C2 C2 C2 B3 C3 C3 C3 C3 B4 C4 C4 C4 C4 B5 C5 C5 C5 C5 B6 C6 C6 C6 C6
MSB
B0 X0 X0 X0 X0
B7 0 0 0 0
B0 C0 C0 C0 C0 C0 C1
B7 C7 C7 C7 C7
C5 C10 C15 C20 C25 C30 C6 C11 C16 C21 C26 C31 C7 C12 C17 C22 C27 C32 C8 C13 C18 C23 C28 C33 C9 C14 C19 C24 C29 C34 C5 C10 C15 C20 C25 C30 C6 C11 C16 C21 C26 C31 C7 C12 C17 C22 C27 C32 C8 C13 C18 C23 C28 C33 C9 C14 C19 C24 C29 C34 C1 G2 C2 G3 C3 G4 C4 G5 C5 G6 C6 G7
5 CGRAM data write 1
X0
X1
X2
X3
1
0
1
0
C2 C3 C4 C0 C1
6 CGRAM data write 2
X0
X1
X2
X3
0
1
1
0
C2 C3 C4
* * * * * * * * * *
C7
2nd byte 3rd byte 4th byte 5th byte 6th byte 2nd byte 3rd byte 4th byte 5th byte 6th byte
7 ADRAM data write 8 Display blink position set
X0 SG S
X1 AD
X2
X3
1 0 1 0 1 0 1 0
1 0 0 1 1 0 0 1
1 0 0 0 0 1 1 1
0 1 1 1 1 1 1 1
C0 G1
* * *
P3 D2 K2
* * *
P4 D3 K3
G8 2nd byte
G9 G10 G11 G12 G13 G14 G15 G16 3rd byte
9 DCRAM address shift A DCRAM address reset C Display duty set D Number of digits set E All lights ON/OFF Test mode
*
D0 K0 L
* *
P2 D1 K1 H
*
Xn Cn SG AD Gn S Pn Dn Kn H L
B General output port set P1
*
*
When data is written to RAM (DCRAM, CGRAM, ADRAM) continuously, addresses are internally incremented automatically. Therefore it is not necessary to specify the 1st byte to write RAM data for the 2nd and later bytes. Note: The test mode is used for inspection before shipment. It is not a user function.
: : : : : : : : : : : :
Don't care Address specification for each RAM Character code specification for each RAM SEG display area specification AD display area specification Display blink position specification Left and right display shift specification General output port status specification Display duty specification Number of digits specification All lights ON instruction All lights OFF instruction
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Semiconductor Positional Relationship Between SEGn and ADn (one digit)
C0
AD1
MSM9200-XX
C1
AD2
C2
AD3
C3
AD4
C4
AD5
C5
AD6
C6
AD7
C7
AD8
Area for the ADRAM data to be output C4
SEG5
C0
SEG1
C1
SEG2
C2
SEG3
C3
SEG4
C5
SEG6
C6
SEG7
C7
SEG8
C8
SEG9
C9
SEG10
C10
SEG11
C11
SEG12
C12
SEG13
C13
SEG14
C14
SEG15
C15
SEG16
C16
SEG17
C17
SEG18
C18
SEG19
C19
SEG20
C20
SEG21
C21
SEG22
C22
SEG23
C23
SEG24
C24
SEG25
C25
SEG26
C26
SEG27
C27
SEG28
C28
SEG29
C29
SEG30
C30
SEG31
C31
SEG32
C32
SEG33
C33
SEG34
C34
SEG35
CGRAM written data. Corresponds to 2nd byte CGRAM written data. Corresponds to 3rd byte CGRAM written data. Corresponds to 4th byte
CGRAM written data. Corresponds to 6th byte CGRAM written data. Corresponds to 5th byte
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Semiconductor Data Transfer System and Command Write System Display control command and data are written by an 8-bit serial transfer. Write timing is shown in the figure below.
MSM9200-XX
Setting the CS pin to "Low" level enables a data transfer. Data is 8 bits and is sequentially input into the DA pin from LSB (LSB first). As shown in the figure below, data is read by the shift register at the rising edge of the shift clock, which is input into the CP pin. If 8-bit data is input, internal load signals are automatically generated and data is written to each register and RAM. Therefore it is not necessary to input load signals from the outside. Setting the CS pin to "High" disables data transfer. Data input from the point when the CS pin changes from "High" to "Low" is recognized in 8-bit units.
CS CP tDOFF tCSH
DA
B0 B1 B2 B3 B4 B5 B6 B7 LSB 1st byte MSB
B0 B1 B2 B3 B4 B5 B6 B7 LSB 2nd byte MSB
B0 B1 B2 B3 B4 B5 B6 B7 LSB 2nd byte MSB
When data is written to DCRAM* Command and address data
Character code data
Character code data of the next address
*
When data is written to RAM (DCRAM, ADRAM, CGRAM) continuously, addresses are internally incremented automatically. Therefore it is not necessary to specify the 1st byte to write RAM data for the 2nd and later bytes.
Reset Function Reset is executed when the RESET pin is set to "L", (when turning power on, for example,) and initializes all functions. Initial status is as follows. * Address of each RAM .................. address "00"H * Data of each RAM ........................ All contents are undefined * Display blink ................................. Blinking is disabled for all outputs * General output port ..................... All general output ports go "Low" * Display digit .................................. 16 digits * Contrast adjustment ..................... 0/16 * All display lights ON or OFF ..... OFF mode * Segment output ............................ All segment outputs go "Low" * AD output ..................................... All AD outputs go "Low" Reset again according to "Initial Setting Flowchart" after reset.
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Semiconductor Description of Commands and Functions
MSM9200-XX
1. DCRAM data write 1 (Specifies the address (00H to 0FH) of DCRAM and writes the character code of CGROM and CGRAM.) 2. DCRAM data write 2 (Specifies the address (10H to 1FH) of DCRAM and writes the character code of CGROM and CGRAM.) 3. DCRAM data write 3 (Specifies the address (20H to 2FH) of DCRAM and writes the character code of CGROM and CGRAM.) 4. DCRAM data write 4 (Specifies the address (30H to 3FH) of DCRAM and writes the character code of CGROM and CGRAM.) DCRAM (Data Control RAM) has a 6-bit address to store character code of CGROM and CGRAM. (4 bits can be set by the user and the 2 bits on the MSB side are automatically set.) The character code specified by DCRAM is converted to a 57 dot matrix character pattern via CGROM or CGRAM. The capacity is 648 bits, which can store 64 characters. Note: The addresses 00H to 3FH of DCRAM are automatically incremented. [Command format]
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 1st byte (1st) X0 X1 X2 X3
LSB
1
0
0
0
MSB
: selects DCRAM data write mode and specifies DCRAM address (Ex: Specifies DCRAM address 00H) : specifies character code of CGROM and CGRAM : written into DCRAM address 00H
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (2nd) C0 C1 C2 C3 C4 C5 C6 C7
To specify the character code of CGROM and CGRAM continuously to the next address, specify only character code as follows. The addresses of DCRAM are automatically incremented. Specification of an address is unnecessary.
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Semiconductor
LSB MSB
MSM9200-XX
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (3rd) C0 C1 C2 C3 C4 C5 C6 C7
LSB MSB
: specifies character code of CGROM and CGRAM : written into DCRAM address 01H
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (4th) C0 C1 C2 C3 C4 C5 C6 C7 : specifies character code of CGROM and CGRAM : written into DCRAM address 02H
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (17th) C0 C1 C2 C3 C4 C5 C6 C7
LSB MSB
: specifies character code of CGROM and CGRAM : written into DCRAM address 0FH
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (18th) C0 C1 C2 C3 C4 C5 C6 C7 : specifies character code of CGROM and CGRAM : written into DCRAM address 10H
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (65th) C0 C1 C2 C3 C4 C5 C6 C7
LSB MSB
: specifies character code of CGROM and CGRAM : written into DCRAM address 3FH
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (66th) C0 C1 C2 C3 C4 C5 C6 C7 : specifies character code of CGROM and CGRAM : DCRAM address 00H is rewritten
X0 (LSB) to X3 (MSB): DCRAM addresses (4 bits: 16 characters) Note: A total of 64 characters for the four specifications C0 (LSB) to C7 (MSB): Character code of CGROM and CGRAM (8 bits: 256 character) [COM positions and set DCRAM addresses] The states when RESET is input and DCRAM address reset commands are executed
Command No. HEX K0 K1 K2 K3 00 01 1 0E 0F 10 11 2 1E 1F 0 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 1 1 0 0 1 1 0 0 4 3E 3F 0 1 1 1 1 1 1 1 COM15 COM16 0 1 0 0 0 0 0 0 COM position COM1 COM2 3 2E 2F 30 31 1 1 0 1 1 1 0 0 1 1 0 0 1 1 0 0 Command No. HEX K0 K1 K2 K3 20 21 0 1 0 0 0 0 0 0 COM position
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Semiconductor
MSM9200-XX
5. CGRAM data write 1 (Specifies the addresses 00H to 0FH of CGRAM and writes character pattern data.) 6. CGRAM data write 2 (Specifies the addresses 10H to 1FH of CGRAM and writes character pattern data.) CGRAM (Character Generator RAM) has a 5-bit address to store 57 dot matrix character patterns. (4 bits can be set by the user and the 1 bit on the MSB is automatically set.) A character pattern stored in CGRAM can be displayed by specifying the character code (address) by DCRAM. The address of CGRAM is assigned to 00H to 1FH. (All the other addresses are the CGROM addresses.) Capacity is (162)358 bits, which can store 32 types of character patterns. Note: The addresses 00H to 1FH of CGRAM are automatically incremented. [Command format]
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 1st byte (1st) X0 X1 X2 X3
LSB
1
0
1
0
MSB
: selects CGRAM data write mode and specifies CGRAM address. (Ex: specifies CGRAM address 00H) : specifies 1st column data : rewritten into CGRAM address 00H
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (2nd) C0 C5 C10 C15 C20 C25 C30
LSB
*
MSB
B0 B1 B2 B3 B4 B5 B6 B7 3rd byte (3rd) C1 C6 C11 C16 C21 C26 C31
LSB
*
MSB
: specifies 2nd column data : rewritten into CGRAM address 00H
B0 B1 B2 B3 B4 B5 B6 B7 4th byte (4th) C2 C7 C12 C17 C22 C27 C32
LSB
*
MSB
: specifies 3rd column data : rewritten into CGRAM address 00H
B0 B1 B2 B3 B4 B5 B6 B7 5th byte (5th) C3 C8 C13 C18 C23 C28 C33
LSB
*
MSB
: specifies 4th column data : rewritten into CGRAM address 00H
B0 B1 B2 B3 B4 B5 B6 B7 6th byte (6th) C4 C9 C14 C19 C24 C29 C34
*
: specifies 5th column data : rewritten into CGRAM address 00H
To specify character pattern data continuously to the next address, specify only character pattern data as follows. The addresses of CGRAM are automatically incremented. Specification of an address is therefore unnecessary. The 2nd to 6th byte (character pattern data) are regarded as one data item, so 300 ns is sufficient for tDOFF time between bytes.
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Semiconductor
LSB MSB
MSM9200-XX
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (7th) C0 C5 C10 C15 C20 C25 C30
LSB
*
MSB
: specifies 1st column data : rewritten into CGRAM address 01H
B0 B1 B2 B3 B4 B5 B6 B7 6th byte (11th) 2nd byte (12th) C4 C9 C14 C19 C24 C29 C34
LSB
*
MSB
: specifies 5th column data : rewritten into CGRAM address 01H : specifies 1st column data : rewritten into CGRAM address 02H
B0 B1 B2 B3 B4 B5 B6 B7 C0 C5 C10 C15 C20 C25 C30
LSB
*
MSB
B0 B1 B2 B3 B4 B5 B6 B7 6th byte (16th) C4 C9 C14 C19 C24 C29 C34
*
MSB
: specifies 5th column data : rewritten into CGRAM address 02H
LSB
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (77th) C0 C5 C10 C15 C20 C25 C30
LSB
*
MSB
: specifies 1st column data : rewritten into CGRAM address 0FH
B0 B1 B2 B3 B4 B5 B6 B7 6th byte (81th) 2nd byte (82th) C4 C9 C14 C19 C24 C29 C34
LSB
*
MSB
: specifies 5th column data : rewritten into CGRAM address 0FH : specifies 1st column data : rewritten into CGRAM address 10H
B0 B1 B2 B3 B4 B5 B6 B7 C0 C5 C10 C15 C20 C25 C30
LSB
*
MSB
B0 B1 B2 B3 B4 B5 B6 B7 6th byte (86th) C4 C9 C14 C19 C24 C29 C34
*
MSB
: specifies 5th column data : rewritten into CGRAM address 10H
LSB
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (157th) C0 C5 C10 C15 C20 C25 C30
LSB
*
MSB
: specifies 1st column data : rewritten into CGRAM address 1FH
B0 B1 B2 B3 B4 B5 B6 B7 6th byte (161th) 2nd byte (162th) C4 C9 C14 C19 C24 C29 C34
LSB
*
MSB
: specifies 5th column data : rewritten into CGRAM address 1FH : specifies 1st column data (CGRAM address 00H is rewritten)
B0 B1 B2 B3 B4 B5 B6 B7 C0 C5 C10 C15 C20 C25 C30
LSB
*
MSB
B0 B1 B2 B3 B4 B5 B6 B7 6th byte (167th) C4 C9 C14 C19 C24 C29 C34
*
: specifies 5th column data (CGRAM address 00H is rewritten)
X0 (LSB) to X3 (MSB): CGRAM addresses (4 bits: 16 characters) Note: A total of 32 characters for the two specifications. C0 (LSB) to C34 (MSB): Character pattern data (35 bits: 35 outputs per digit) 19/34
Semiconductor
MSM9200-XX
Positional relationship between the output area of CGROM and that of CGRAM
C0 C5 C10 C15 C20 C25 C30 area that corresponds to 2nd byte (1st column) area that corresponds to 3rd byte (2nd column) C1 C6 C11 C16 C21 C26 C31 C2 C7 C12 C17 C22 C27 C32 C3 C8 C13 C18 C23 C28 C33 C4 C9 C14 C19 C24 C29 C34 area that corresponds to 6th byte (5th column) area that corresponds to 5th byte (4th column) area that corresponds to 4th byte (3rd column)
Note: CGROM (Character Generator ROM) has an 8-bit address to generate 57 dot matrix character patterns. The capacity is 224358 bits, which can store 224 types of character patterns. 2 types of general-purpose code are availble (see ROM CODE list) and custom codes are provided on customer's request.
[CGROM addresses and set CGRAM addresses] Refer to ROMCODE table
Command No. HEX K0 K1 K2 K3 00 01 02 03 04 05 06 2 07 08 09 0A 0B 0C 0D 0E 0F 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 CGROM address RAM00(00000000B) RAM01(00000001B) RAM02(00000010B) RAM03(00000011B) RAM04(00000100B) RAM05(00000101B) RAM06(00000110B) RAM07(00000111B) RAM08(00001000B) RAM09(00001001B) 4 Command No. HEX K0 K1 K2 K3 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 CGROM address RAM10(00010000B) RAM11(00010001B) RAM12(00010010B) RAM13(00010011B) RAM14(00010100B) RAM15(00010101B) RAM16(00010110B) RAM17(00010011B) RAM18(00011000B) RAM19(00011001B)
1 RAM0A(00001010B) 1 RAM0B(00001011B) 1 RAM0C(00001100B) 1 RAM0D(00001101B) 1 1 RAM0E(00001110B) RAM0F(00001111B)
1 RAM1A(00011010B) 1 RAM1B(00011011B) 1 RAM1C(00011100B) 1 RAM1D(00011101B) 1 1 RAM1E(00011110B) RAM1F(00011111B)
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Semiconductor 7. ADRAM data write (specifies address of ADRAM and writes symbol data)
MSM9200-XX
ADRAM (Additional Data RAM) has a 4-bit address to store symbol data. Symbol data specified by ADRAM is directly output without CGROM and CGRAM. The capacity is 816 bits, which can store 8 types of symbol patterns for each digit. The terminal to which the contents of ADRAM are output can be used as a cursor. [Command format]
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 1st byte (1st) X0 X1 X2 X3
LSB
1
1
1
0
MSB
: selects ADRAM data write mode and specifies ADRAM address (Ex: specifies ADRAM address 0H) : sets symbol data (written into ADRAM address 0H)
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (2nd) C0 C1 C2 C3 C4 C5 C6 C7
To specify symbol data continuously to the next address, specify only symbol data as follows. The address of ADRAM is automatically incremented. Specification of addresses is therefore unnecessary.
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (3rd) 2nd byte (4th) C0 C1 C2 C3 C4 C5 C6 C7
LSB MSB
: sets symbol data (written into ADRAM address 1H) : sets symbol data (written into ADRAM address 2H)
B0 B1 B2 B3 B4 B5 B6 B7 C0 C1 C2 C3 C4 C5 C6 C7
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (17th) 2nd byte (18th) C0 C1 C2 C3 C4 C5 C6 C7
LSB MSB
: sets symbol data (written into ADRAM address FH) : sets symbol data (ADRAM address 00H is rewritten.)
B0 B1 B2 B3 B4 B5 B6 B7 C0 C1 C2 C3 C4 C5 C6 C7
X0 (LSB) to X3 (MSB): ADRAM addresses (4 bits: 16 characters) C0 (LSB) to C7 (MSB): Symbol data (8-symbol data per digit)
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Semiconductor [COM positions and ADRAM addresses]
HEX D0 D1 D2 D3 0 1 2 3 4 5 6 7 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 COM position COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 HEX D0 D1 D2 D3 8 9 A B C D E F 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
MSM9200-XX
COM position COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16
8. Display blink position set (sets the blink position for the SEG area or AD area in COMn. Display blink position can be set separately for the SEG area and AD area. In this case, select by command in which COMn the SEG area or AD area is made blink. The blink disabled state is entered for this setting when power is turned on or when a RESET signal is input. The display blink cycle is determined by the frequency to be input to the BLINK pin. [Command format]
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 1st byte (1st) SG AD
LSB
**
0
0
0
1
MSB
: selects either the AD output area or the segment output area and specifies digit
B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (2nd) G1 G2 G3 G4 G5 G6 G7 G8
LSB MSB
: specifies blink position to COM1 to COM8
B0 B1 B2 B3 B4 B5 B6 B7 3rd byte (3rd) G9 G10 G11 G12 G13 G14 G15 G16 : specifies blink position to COM9 to COM16
The 2nd and 3rd bytes (COM1 to COM16 position specification) are regarded as one data item, so 300 ns is sufficient for tDOFF time between bytes. SG: Specifies SEG area AD: Specifies AD area Gn: Specifies blinks
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Semiconductor
MSM9200-XX
[SEG and AD display and set data]
SG/AD 0 0 1 1 Gn 0 1 0 1 SEG and AD display Does not blink (current state) Does not bilnk (current state) Specified positions do not blink Specified positions blink (The state when power is applied or when RESET is input)
Note: If both SG and AD are set to "1" by command, both the SEG area and the AD area are specified.
9. DCRAM address shift (Shifts SEG output left or right.) DCRAM address shift shifts SEG output 1 digit to the left or right using 1 bit data. AD output cannot be shifted. [Command format]
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 1st byte SG
***
1
0
0
1
: selects DCRAM address shift and sets shift value (left, right)
S: Specifies the direction of shift [Set data and shift direction of display]
S 0 1 Shift direction of display Shift to left Shift to right
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Semiconductor [DCRAM address shift and COM positions] When S=0 (shift to left) is performed from the initial state.
Command No. COM position COM2 COM3 3 0E 0F 10 11 2 1E 1F 0 1 1 1 1 1 1 1 0 1 0 1 1 1 0 0 1 1 0 0 1 1 0 0 4 3E 3F 0 1 1 1 1 1 1 1 COM16 2E 2F 30 31 0 1 0 1 1 1 0 0 1 1 0 0 1 1 0 0 Command No.
MSM9200-XX
HEX K0 K1 K2 K3 00 01 0 1 0 0 0 0 0 0
HEX K0 K1 K2 K3 20 21 0 1 0 0 0 0 0 0
COM position
1
COM1
When S=1 (shift to right) is performed from the initial state.
Command No. COM position COM1 3 0E 0F 10 11 2 1E 1F 0 1 1 1 1 1 1 1 0 1 0 1 1 1 0 0 1 1 0 0 1 1 0 0 4 3E 3F 0 1 1 1 1 1 1 1 COM14 COM15 COM16 2E 2F 30 31 0 1 0 1 1 1 0 0 1 1 0 0 1 1 0 0 Command No. COM position
HEX K0 K1 K2 K3 00 01 0 1 0 0 0 0 0 0
HEX K0 K1 K2 K3 20 21 0 1 0 0 0 0 0 0
1
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Semiconductor A. DCRAM address reset (returns display status to initial setting status)
MSM9200-XX
The DCRAM address reset returns the status where a DCRAM address shift is executed to initial status. [Command format]
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 1st byte
****
0
1
0
1
: selects DCRAM address reset
Relation between the DCRAM address shifts and the COM outputs
Initial status or the status where display address reset executed (DCRAM address is 00H) COM output DCRAM address (HEX) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
When left shift is executed in the initial status COM output DCRAM address (HEX) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 3F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E
When right shift is executed in the initial status COM output DCRAM address (HEX) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
B. General output port set (specifies the general output port status) The general output port is an output for 4-bit static operation. It is used to control other I/O devices and turn on LED. When at the "High" level, this output becomes the VDD voltage, and when at the "Low" level, it becomes the ground potential. Therefore, the fluorescent display tube cannot be driven. [Command format]
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 1st byte P1 P2 P3 P4 1 1 0 1 : selects a general output port and specifies the output status
P1-P4: general output port [Set data and set state of general output port]
Pn 0 1 Display state of general output port Sets to the output to Low Sets to the output to High (The state when power is applied or when RESET is input.)
25/34
Semiconductor C. Display duty set (writes display duty value to duty cycle register)
MSM9200-XX
Display duty adjusts contrast in 16 stages using 4-bit data. When power is turned on or when the RESET signal is input, the duty cycle register value is "0". Always execute this instruction before turning the display on, then set a desired duty value. [Command format]
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 1st byte D0 D1 D2 D3 0 0 1 1 : selects display duty set mode and sets duty value
D0 (LSB) to D3 (MSB): display duty data (4 bits: 16 stages) [Relation between setup data and controlled COM duty]
HEX *0 1 2 3 4 5 6 7 D3 0 0 0 0 0 0 0 0 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 COM duty 0/16 1/16 2/16 3/16 4/16 5/16 6/16 7/16 HEX 8 9 A B C D E F D3 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 COM duty 8/16 9/16 10/16 11/16 12/16 13/16 14/16 15/16
*
The state when powered on or when RESET signal inputs.
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Semiconductor D. Number of digits set (writes the number of display digits to the display digit register)
MSM9200-XX
The number of digits set can display a maximum of 16 digits using 4-bit data. When power is turned on or when a RESET signal is input, the number of digit register value is "0". Always execute this instruction to change the number of digits before turning the dispaly on. [Command format]
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 1st byte K0 K1 K2 K3 1 0 1 1 : selects the number of digit set mode and specifies the number of digit value
K0 (LSB) to K3 (MSB): number of digit data (4 bits: 16 digits) [Relation between setup data and controlled COM]
HEX 0 1 2 3 4 5 6 7 K3 0 0 0 0 0 0 0 0 K2 0 0 0 0 1 1 1 1 K1 0 0 1 1 0 0 1 1 K0 0 1 0 1 0 1 0 1 Number of digits of COM COM1-16 COM1-1 COM1-2 COM1-3 COM1-4 COM1-5 COM1-6 COM1-7 HEX 8 9 A B C D E F K3 1 1 1 1 1 1 1 1 K2 0 0 0 0 1 1 1 1 K1 0 0 1 1 0 0 1 1 K0 0 1 0 1 0 1 0 1 Number of digits of COM COM1-8 COM1-9 COM1-10 COM1-11 COM1-12 COM1-13 COM1-14 COM1-15
E. All display lights ON/OFF set (turns all dispaly lights ON or OFF) All display lights ON is used primarily for display testing. All display lights OFF is primarily used to prevent malfunction when power is turned on. [Command format]
LSB MSB
B0 B1 B2 B3 B4 B5 B6 B7 1st byte L H
**
0
1
1
1
: selects all display lights ON or OFF mode and sets all lights ON or OFF value
[Set data and display state of SEG and AD]
L 0 1 0 1 H 0 0 1 1 Display state of SEG and AD All outputs maintain current states Sets all outputs to Low Sets all outputs to High Sets all outputs to High (All lights ON mode has priority.) (The state when power is applied or when RESET is input.)
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Semiconductor Initial Setting Flowchart
MSM9200-XX
Apply VFL
All display lights OFF
Status of all outputs by RESET signal input
General output port set
Number of digits set
Display duty set Select a RAM to be used
DCRAM Data write mode (with address set)
Address is automatically incremented
CGRAM Data write mode (with address set)
Address is automatically incremented
ADRAM Data write mode (with address set)
Address is automatically incremented
DCRAM Character code DCRAM Is character code write ended?
YES
CGRAM Character code CGRAM Is character code write ended?
YES
ADRAM Character code ADRAM Is character code write ended?
YES
NO
NO
NO
YES
Another RAM to be set?
Releases all display lights OFF mode
Display operation mode
End
28/34
Semiconductor
MSM9200-XX
APPLICATION CIRCUIT
Heater transformer 57-dot matrix fluorescent display tube
ANODE ANODE GRID (SEGMENT) (SEGMENT) (DIGIT) R2 VDD C2 VDD C3 MCU Output port GND CS CP DA BLINK 8 RESET VDD, AD1-8 VDISP1-3 35 SEG1-35 16 COM1-16 R4 LED P1-4 GND VFL1-2 OSC0 OSC1 R1 C1 4 NPN Tr GND VDD
MSM9200-XX
R3 VFL C4 ZD
Notes: 1. The VDD value depends on the power supply voltage of the microcontroller used. Adjust the values of the constants R1, R2, R4, C1, and C2 to the power supply voltage used. 2. The VFL value depends on the fluorescent display tube used. Adjust the values of the constants R3 and ZD to the power supply voltage used.
29/34
Semiconductor Reference data
MSM9200-XX
The figure below shows the relationship between the VFL voltage and the output current of each driver. Take care that the total power consumtion to be used does not exceed the power dissipation.
[VFL Voltage-Output Current of Each Driver] (mA) -30 -25
COM1 to COM16 (Condition: VOH=VDISP-1.5 V)
[Output Current] (mA)
-20 -15 -10 -5 0 -10 AD1 to AD8 (Condition: VOH=VDISP-1.5 V) SEG1 to SEG35 (Condition: VOH=VDISP-1.5 V)
-20
-30
-40
-50
-60 (V)
[VFL Voltage (VDD-n) ]
30/34
Semiconductor
MSM9200-XX
MSM9200-01 ROM Code
00000000B (00H) to 00011111B (1FH) are the CGRAM addresses.
MSB 0000 LSB 0000 RAM00 RAM10 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
0001 RAM01 RAM11
0010 RAM02 RAM12
0011 RAM03 RAM13
0100 RAM04 RAM14
0101 RAM05 RAM15
0110 RAM06 RAM16
0111 RAM07 RAM17
1000 RAM08 RAM18
1001 RAM09 RAM19
1010 RAM0A RAM1A
1011 RAM0B RAM1B
1100 RAM0C RAM1C
1101 RAM0D RAM1D
1101 RAM0E RAM1E
1111 RAM0F RAM1F
31/34
Semiconductor
MSM9200-XX
MSM9200-02 ROM Code
00000000B (00H) to 00011111B (1FH) are the CGRAM addresses.
MSB 0000 LSB 0000 RAM00 RAM10 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
0001 RAM01 RAM11
0010 RAM02 RAM12
0011 RAM03 RAM13
0100 RAM04 RAM14
0101 RAM05 RAM15
0110 RAM06 RAM16
0111 RAM07 RAM17
1000 RAM08 RAM18
1001 RAM09 RAM19
1010 RAM0A RAM1A
1011 RAM0B RAM1B
1100 RAM0C RAM1C
1101 RAM0D RAM1D
1101 RAM0E RAM1E
1111 RAM0F RAM1F
32/34
Semiconductor Digit Output Timing (for 16-digit display, at a duty of 15/16)
MSM9200-XX
T=8/ fOSC
Frame cycle t1=1024T Display timing t2=60T Blank timing t3=4T
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 AD1-8 SEG1-35
(t1=4.096 ms when fosc=2.0 MHz) (t2=240 ms when fosc=2.0 MHz) (t3=16 ms when fosc=2.0 MHz)
VDISP VFL
VDISP VFL
33/34
Semiconductor
MSM9200-XX
PACKAGE DIMENSIONS
(Unit : mm) QFP80-P-1414-0.65-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.85 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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